1. Field of the Invention
The present invention is related to synchronization of reset signals.
2. Background Art
Integrated circuit chips typically include circuits that can be reset by one or more reset signals. The reset signals include hardware-based reset signals and/or software-based reset signals. Reset signals can be active low or active high. Active low reset signals reset circuits when the reset signal goes low. Active high reset signals reset circuits when the reset signal goes high. The following discussion applies to active low and active high reset signals.
Reset signals can be used in synchronous and/or asynchronous systems. In synchronous systems, reset signals take effect on a clock cycle subsequent to the reset signal. In asynchronous systems, reset signals take effect immediately, without regard to a clock cycle.
When a synchronous system is to be reset, the reset signal needs to go away at a good time relative to a local clock signal that drives the circuit. For example, a trailing or rising edge of an active low reset signal should not occur near a transition of the clock signal. Otherwise, the reset signal may not be adequately captured by the circuit. If the reset signal is not adequately captured by the circuit, a timing violation occurs that can cause instability within the circuit and/or cause a test of the system to fail. Thus, reset signals should be synchronized with the local clock so that the reset signal occurs sufficiently between rising edges of the local clock.
There are a number of situations where a reset signal may not be properly synchronized with a local clock signal. One situation is where a reset signal is generated in a first clock domain having a first frequency, but is used in a second clock domain having a second frequency. Another situation is where there is delay between a reset signal generator and a circuit that utilizes the reset signal. The delay can be the result of physical distance between the reset signal generator and the circuit that utilizes the reset signal. Alternatively, or additionally, the delay can be the result of circuit components coupled between the reset signal generator and the circuit that utilizes the reset signal
Therefore, what is needed is a system and method to synchronize a reset signal with a local clock.